1. Field of the Invention
The present invention relates to semiconductor devices such as semiconductor packages, particularly relates to thin and highly reliable semiconductor packages.
2. Description of the Related Art
As electronic instruments become compact, development of a technology packaging various kinds of electronic components in high density into electronic instruments is being in progress. Further, upon packaging the electronic components with high density, the electronic components such as semiconductor packages and the like are desired to be made smaller and thinner. This is because, in order to realize a compact and highly functional electronic instrument, not only improvement of integration of a semiconductor element but also compactness of a semiconductor package in which a semiconductor element is packaged are required. In order to correspond to such a requirement, various types of thin semiconductor packages are being proposed.
A means for mounting a semiconductor element on a wiring substrate can be generally divided into a face-up type bonding (wire bonding), and face-down type bonding (flip chip bonding).
In the face-up type mounting, connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with bonding wires. Then, by molding the semiconductor element including the bonding wires on the wiring substrate, a semiconductor package is formed.
On the other hand, in the face-down type mounting, connecting electrodes of a semiconductor element and connecting electrodes of a wiring substrate are connected with conductive bumps and the like.
In the semiconductor package of the flip chip type, there are an over-coat type in which a semiconductor element is molded as a whole, and a bare chip type in which a semiconductor element is exposed. Even in the latter case, it is generally done to seal a gap between a semiconductor element and a wiring substrate with a resin and the like. Semiconductor packages of the flip chip type, because they can be made thinner than those of the face-up type, are recently used much in CSP(Chip Size Package) and the like. The CSPs are used much in, for instance, computers, semiconductor packages of high frequency and integrated function used in communication instruments, or portable information instruments such as a PDA.
FIG. 11 is a diagram showing a structure of a conventional semiconductor package.
In the semiconductor package 90 illustrated in FIG. 11, a semiconductor element (chip) 92 is mounted in a face-down manner on a wiring substrate 91. Connecting terminals 92a of the semiconductor element 92 and pads 93 disposed on the wiring substrate 91 are connected with conductive bumps 94. The conductive bumps are composed of, for instance, solder, gold and the like.
Further, a gap between the wiring substrate 91 and the semiconductor element 92 is sealed with a resin layer 95 called an under-fill. Here, a semiconductor package of a structure in which a rear surface of the semiconductor 92 is exposed is illustrated, however, if the semiconductor element 92 is covered with a molding resin as a whole, a semiconductor package of the over-coat structure can be obtained.
Further, on the rear surface of the semiconductor mounting surface of the wiring substrate 91, connecting pads 96 connected to the bonding pads 93 are disposed, on the connecting pads 96 solder balls 97 are disposed. Those solder balls 97 and the conductive bumps 94 are connected electrically with interior wiring.
In the wiring substrate 91, glass fabric based epoxy resin is employed as an insulating layer. As the wiring substrate 91, that of two-layered structure is employed here, however, that of multi-layered structure such as three-layered structure or more may be employed. Further, on the rear surface (upper surface) of the semiconductor chip, a metallic cap or a heat-sink is disposed in some cases.
Further, the solder balls are disposed as BGA (ball grid array) type terminals. Incidentally, the connecting terminals 96 to which the solder balls 97 are disposed and the bonding pads 93 of the wiring substrate are connected between layers with, for instance, through holes, conductive pillars consisting of conductive resin and the like.
FIG. 12A, FIG. 12B and FIG. 12C are diagrams explaining a method forming a resin layer 95 (under-fill).
First, on the circumference of a semiconductor element 92, a liquid resin 95i such as epoxy resin or the like is supplied from a dispense nozzle 99. Viscosity of the resin is selected and adjusted according to demands. The dispense nozzle 99 is attached to a syringe in which the resin 95i is stocked. The resin 95i permeates into a gap between the wiring substrate 91 and the semiconductor element 92 due to capillary action (FIG. 12A). That is, the resin 95i supplied from the dispense nozzle 99 is dripped on the circumference of the wiring substrate 91 (FIG. 12B), then the dripped resin permeates into the gap between the wiring substrate 91 and the semiconductor element 92 (FIG. 12C), thus the under-fill is formed thereby.
However, such a thin semiconductor package as described above has a problem described in the following. That is, in order to reduce thickness of a semiconductor package as a whole, strength is sacrificed, accordingly the semiconductor package is liable to suffer deformation such as warp and the like.
When such a warp of the semiconductor package occurs, the connecting terminals 96 and the solder balls 97 constituting the BGA, for instance, are not arranged on the same plane, to deteriorate so-called coplanarity. Therefore, there occur such problems that a semiconductor package is made impossible to be packaged on a mother board, or, even after packaging, in the course of time, due to the added thermal load and the like, reliability of connection can not be maintained. Therefore, in the case of a thin semiconductor package being used actually, how to improve productivity and reliability is a problem to be solved.
In the manufacturing steps of a semiconductor package of flip-chip type such as aforementioned, in the step of forming a resin layer 95, the liquid resin is cured thermally in the temperature range of 100 to 180xc2x0 C. Therefore, in the course of returning to room temperature, the semiconductor package suffers warp.
Thermal expansion coefficient of a semiconductor element and that of a wiring substrate differ approximately one digit in general. The thermal expansion coefficient of a semiconductor element (chip) consisting of silicon, for instance, is about 3-4 ppm/K, whereas the thermal expansion coefficient of a wiring substrate having an organic insulating layer such as FR-4, FR-5 or BT resin (Bis maleimide triazine) is about 12 to 20 ppm/K. Therefore, deformation due to thermal load is larger for the wiring substrate than that of the semiconductor chip. Therefore, stress pulling the semiconductor element 92 occurs, due to this stress, the semiconductor package suffers warp.
FIG. 13A, FIG. 13B and FIG. 13C are diagrams explaining stress suffered by a semiconductor package. Here, appearance of chip crack and resin crack observed in TCT (Thermal Cycle Test) which is a generally adopted environment test of semiconductor package is shown schematically.
In this test, a so-called fan-in type semiconductor package, in which a wiring substrate 91 is smaller than a semiconductor element 92, was employed.
On a wiring substrate 91 is mounted a semiconductor element 92, a resin layer 95 is filled in a gap formed between the wiring substrate 91 and the semiconductor element. In general, compared with thicknesses of the wiring substrate 91 and semiconductor element 92, that of an under-fill resin layer 95 is extremely thin.
When the aforementioned thermal load is added on such a semiconductor package, on the rear surface side of the semiconductor element 92 a tensile stress works, due to this stress chip crack occurs (FIG. 13A, FIG. 13B).
Further, even in the case of stiffness of the chip enduring the stress, due to the stress working in a direction to peel a semiconductor element and a wiring substrate, fillet crack occurs (FIG. 13C). Thus, in any cases, due to bimetal structure, warp occurs.
Displacement of warp of a semiconductor package after an under-fill is formed is desirable to be suppressed at 100 xcexcm or less at most, preferable to be 80 xcexcm or less. Further, the displacement of the warp of the semiconductor package is further desirable to be suppressed approximately 50 to 70 xcexcm or less. That is implemented so that there does not occur any inconvenience when solder balls 97 or caps are attached after the under-fill is formed, or package coplanarity guaranty (ordinarily the maximum of 100 xcexcm) is to be satisfied.
For instance, according to the result of simulation of the displacement of the warp caused when a semiconductor element of 20 mm square is mounted on a multi-layered wiring substrate on which a BT of a thickness of 0.8 mm is employed as an insulating layer, approximately 89 xcexcm of displacement of warp is for a chip of a thickness of 0.3 mm, approximately 77 xcexcm for a chip of a thickness of 0.45 mm, and approximately 62 xcexcm for a chip of a thickness of 0.625 mm.
The above described calculation of the coplanarity of the semiconductor package was carried out under the following conditions.
Thermal expansion coefficient of the semiconductor element xcex1c: 3.5[ppm/K],
modulus of elasticity of the semiconductor element: 166[GPa],
thermal expansion coefficient of resin layer (under-fill): 26[ppm/K],
modulus of elasticity of the resin layer (under-fill): 10[GPa},
thermal expansion coefficient of the wiring substrate: 14.6[ppm/K],
modulus of elasticity of the substrate: 24[GPa], and temperature difference between cure temperature (150xc2x0 C.) and room temperature (25xc2x0 C.): 125xc2x0 C.
First, radius of curvature xcfx81 is calculated as follows.
FIG. 15 is a diagram for explaining flexure of a multi-layer composite beam.
Here,
t is a coordinate between t(i+1) and t(i) and corresponds to a displacement in the direction of the thickness of the semiconductor package.
Here,
t1: front surface of resin layer of overcoat(t1=0),
t2: a boundary between the resin layer of the overcoat and the semiconductor element,
t3: a boundary between the semiconductor element and the resin layer of the under-fill,
t4: a boundary between the resin layer of the under-fill and the wiring substrate,
t5: bottom surface of the wiring substrate.
Further,
xcex1i: thermal expansion coefficient of the layer i,
Ei: modulus of elasticity of the layer i,
"sgr"i: thermal stress thereto the layer i is subjected,
xcex5i: thermal strain (displacement) of the layer i,
(txe2x88x92xcex4)/xcfx81: distortion (displacement) due to flexure of the i-th layer,
xcex4i: coordinate of a neutral line,
xcfx81: radius of curvature.
Here, "sgr"i and xcex5i can be expressed with the following equations.
"sgr"i=[xcex5i+(txe2x88x92xcex4)/xcfx81]Ei
xcex5i=[xcexa3Ej(tj+1xe2x88x92tj) (xcex1jxe2x88x92xcex1i)xcex94T]/xcexa3Ej(tj+1xe2x88x92tj)
The neutral line xcex4 and the radius of curvature xcfx81 are expressed, respectively, by
xe2x80x83xcex4=T/S, xcfx81=U/S.
Therefore,
S=xe2x88x926[xcexa3Ejxcex5j(tj+1xe2x88x92tj)xc2x7xcexa3Ej(tj+12xe2x88x92tj2)xe2x88x92xcexa3Ejxcex5j(tj+12xe2x88x92tj2)xc2x7xcexa3Ej(tj+1xe2x88x92tj)],
T=xe2x88x924xcexa3Ejxcex5j(tj+1xe2x88x92tj)xc2x7xcexa3Ej(tj+13xe2x88x92tj3)+3xcexa3Ejxcex5j(tj+12xe2x88x92tj2)xc2x7xcexa3Ej(tj+12xe2x88x92tj2),
and
U=3[xcexa3Ej(tj+12xe2x88x92tj2)]2xe2x88x924xcexa3Ej(tj+13xe2x88x92tj3)xc2x7xcexa3Ej(tj+1xe2x88x92tj).
From the above, the coplanarity of a semiconductor package becomes
xcfx81xe2x88x92xcfx81 cos(L/xcfx81/2)(L is the length of one side of semiconductor package).
When considered dimensional tolerance, approximately 20 xcexcm of allowance is necessary. Therefore, a chip of a standard size of flip-chip (thickness: 0.3 to 0.625 mm) becomes too large in its warp to be capable of securing sufficient accuracy.
Thus, due to discrepancy of the thermal expansion coefficients of constituent elements of a semiconductor package, there occur problems such as destruction and peeling of the semiconductor element, destruction and peeling of the under-fill, or lowering of coplanarity of the semiconductor package. Such problems are becoming problematic as a semiconductor package becomes thinner.
Another problem of the flip-chip type semiconductor package is in its difficulty of securing heat releasing path for a semiconductor element. In the case of a semiconductor element being mounted on a wiring substrate in a face-up way, a rear surface of the semiconductor element (the surface opposite to the surface where integrated circuit is formed) is connected onto die pads of the wiring substrate. Therefore, heat from the semiconductor element can be released to the wiring substrate side.
Whereas, in the case of a semiconductor package of the flip-chip type, heat generated by the semiconductor can not be released easily towards the wiring substrate side. This is because connection between the semiconductor element and the wiring substrate is implemented with fine conductive bumps, and because resin of small thermal conductivity is filled in the gap between the semiconductor element and the wiring substrate.
Therefore, in a semiconductor package of flip-chip type suitable for high density packaging, a technology enabling enhancement of heat release efficiency of a semiconductor element is in strong demand.
The present invention was carried out to solve these problems. That is, an object of the present invention is to provide a semiconductor package which is thin, compact and highly reliable. Further, another object of the present invention is to provide a thin semiconductor package of high connection reliability. Still another object of the present invention is to provide a semiconductor package of a structure suitable for high density packaging.
In order to solve such problems, a semiconductor package of the present invention adopts such a configuration as described below.
The first aspect of a semiconductor package of the present invention Comprises, a wiring substrate having a first face and a second face, the first face having a first area and a second area surrounds the first area, and at least a first connecting pad arranged in the first area; a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type; at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and, a resin layer disposed on the first face of the wiring substrate, the resin layer disposed so that the second face of the semiconductor element being exposed, side faces of the semiconductor element being sealed, and a gap between the first face of the wiring substrate and the first face of the semiconductor element being filled.
It is also possible to comprises a wiring substrate which has a first face having a first area thereon a first connecting pads are disposed and a second area in the circumference of the first area and a second face; a semiconductor element which has a first face thereon connecting terminals are disposed and a second face, and is mounted in a face-down way on the first area of the first face of the wiring substrate; conductive bumps connecting the first connecting pads of the wiring substrate and connecting terminals of the semiconductor element; and a resin layer for sealing disposed such that the second face of the semiconductor element is exposed, and side surface of the semiconductor element is covered, and the resin layer fills a gap between the semiconductor element and the wiring substrate.
In the semiconductor package of the present invention, the resin layer for sealing may have a first face substantially in parallel with the first face of the wiring substrate, in addition, may be disposed such that the first face of the resin layer for sealing and the second face of the semiconductor element are substantially in a same plane.
In addition, the resin layer for sealing may be inclined in its side faces, and, at the same time, the first face of the wiring substrate can be made larger than the first face of the resin layer for sealing.
Further, the resin layer for sealing may be disposed so that it covers substantially the second area of the first face of the wiring substrate.
The semiconductor package of the present invention may further comprise a conductive plate on the second face of the semiconductor element. By disposing such a configuration, a heat releasing path of the semiconductor element can be secured. Therefore, reliability of the semiconductor package can be improved. Further, thermal load being put on the semiconductor package can be alleviated. Therefore, the stress generated due to discrepancy and the like of thermal expansion coefficients of the constituent elements such as a semiconductor element, a resin layer for sealing and a wiring substrate on the semiconductor package, can be alleviated. Therefore, a thin semiconductor package of high dimensional accuracy can be provided.
It is desirable to connect the conductive plate and the second face of the semiconductor element with a conductive resin. Since the conductive resin is high in its thermal conductivity, the heat of the semiconductor element can be effectively released outsides.
Further, the resin layer for sealing may be disposed such that it covers the side faces of the conductive plate. That is, with the resin layer for sealing, the conductive plate may be fixed. In this case, it is desirable from the view-point of securing heat releasing path to dispose the sealing resin layer with the conductive plate exposed.
Incidentally, the second face of the semiconductor element may be disposed with not only the conductive plate but also a heat releasing plate with a heat-sink, for instance.
The second aspect of a semiconductor package of the present invention comprises, a wiring substrate having a first face and a second face, the substrate having at least a first connecting pad formed on the first face; a semiconductor element having a first face and a second face, the semiconductor element having at least a connecting terminal formed on the first face, and the semiconductor element being mounted on the first area of the wiring substrate in a face-down type; at least a conductive bump connecting the first connecting pad of the wiring substrate and the connecting terminal of the semiconductor element; and, a resin layer disposed on the first face of the wiring substrate and the second face of the semiconductor element so that the semiconductor element being sealed; wherein, (xcex1rxc2x7Erxc2x7Hr)/(xcex1sxc2x7Esxc2x7Hs) is approximately 0.6 or more, when xcex1r is a thermal expansion coefficient of the resin layer, Er is a Young""s modulus if the resin layer, Hr is a thickness of the resin layer, xcex1s is a thermal expansion coefficient of the wiring substrates, Es is a Young""s modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
It is also possible to comprise a wiring substrate having a first face thereon a first connecting pads are disposed and a second face; a semiconductor element which has a first face thereon connecting terminals are disposed and a second face, and is mounted in a face-down way on the first face of the wiring substrate; conductive bumps connecting the first connecting pads of the wiring substrate and the connecting terminals of the semiconductor element; and a resin layer disposed on the first face of the wiring substrate in such a manner that seals the semiconductor element; wherein, when thermal expansion coefficient, Young""s modulus and thickness of the wiring substrate is xcex1s, Es and Hs, respectively, and thermal expansion coefficient, Young""s modulus and thickness of the resin layer is xcex1r, Er and Hr, respectively, (xcex1rxc2x7Erxc2x7Hr)/(xcex1sxc2x7Esxc2x7Hs) is approximately 0.6 or more.
When thermal expansion coefficient and Young""s modulus of the semiconductor is xcex1c, Ec, respectively, (xcex1cxc2x7Ec)/(xcex1sxc2x7Es) may be designed to be approximately 1.5 or more.
The present inventors found that, by adjusting thermal expansion coefficient xcex1s, Young""s modulus Es and thickness Hs of the wiring substrate, and, thermal expansion coefficient xcex1r, Young""s modulus Er and thickness Hr of the resin layer, the stress being put on the semiconductor package can be effectively alleviated. The present invention is based on such findings.
That is, when thermal expansion coefficient, Young""s modulus and thickness of the wiring substrate are xcex1s, Es and Hs, respectively, and thermal expansion coefficient, Young""s modulus and thickness of the resin layer are xcex1r, Er and Hr, respectively, by setting respective parameters for the value of (xcex1rxc2x7Erxc2x7Hr)/(xcex1sxc2x7Esxc2x7Hs) to be approximately 0.6 or more, a semiconductor package of small deformation and high coplanarity can be obtained. Further, reliability during packaging a semiconductor package of the present invention on a mother substrate can be enhanced.
Incidentally, the thickness of a resin layer (under-fill) filled in between a semiconductor element and a wiring substrate is ordinarily extremely thin (for instance, approximately 0.2 mm or less). Therefore, this part exerts very slight influence on the distortion of the whole semiconductor package. Therefore, the thickness Hr of the resin layer is set as a thickness of the resin layer disposed on the second face of the semiconductor element. Further, the resin layer disposed as the under-fill and the resin layer sealing the whole semiconductor element can be composed of different materials.
For instance, the resin layer for sealing may be divided into a first portion filled in between the wiring substrate and the semiconductor element and a second portion covering the semiconductor element from above the second face of the semiconductor element, and the first portion may be constituted of a resin layer of smaller Young""s modulus than that of the second portion. By adopting such a constitution, a soft resin can be disposed in the circumference of the conductive bumps, thereby deformation and rupture of the conductive bumps can be prevented from occurring. Therefore, a semiconductor package of high reliability and high productivity can be provided.
The third aspect of a manufacturing method of a semiconductor package of the present invention comprises, a step of mounting a semiconductor element on a first face of a wiring substrate, a first face of the semiconductor having at least a connecting terminal, the first face of the wiring substrate having at least a first connecting pad, the connecting terminal of the semiconductor element being connected by a conductive bump; and a step of forming a resin layer on the first face of the wiring substrate so that the semiconductor element is sealed; wherein, xcex1r, Er, Hr, xcex1s, Es, Hs are arranged so that (xcex1rxc2x7Erxc2x7Hr)/(xcex1sxc2x7Esxc2x7Hs) is approximately 0.6 or more, when xcex1r is a thermal expansion coefficient of the resin layer, Er is a Young""s modulus if the resin layer, Hr is a thickness of the resin layer, xcex1s is a thermal expansion coefficient of the wiring substrates, Es is a Young""s modulus of the wiring substrate and Hs is a thickness of the wiring substrates.
It is preferable to adjust xcex1r, Er, or Hr of the resin so as to meet the equation.
The step of forming the resin layer can be carried out with transfer molding in which, after setting a wiring substrate mounted a semiconductor element thereon in a cavity, resin is supplied to be cured. Further, in this case, the resin layer may be supplied under pressure, and, at the same time, curing can be carried out thermally.
Further, with tablets of a resin of low melt viscosity such as epoxy based resin, the resin layer may be formed with transfer mold method.
The semiconductor package of the present invention may be provided with a sealing resin body consisting of a first resin layer filling a gap between a first face thereon conductive bumps of a semiconductor element are formed and a main surface of a wiring substrate, and a second resin layer which contacts at least circumference of a semiconductor element, and is formed so as to surround the semiconductor element.
A semiconductor package of the present invention comprises at least one semiconductor element having conductive bumps; a wiring substrate the main surface thereof is electrically connected to the semiconductor element through the conducive bumps; and a sealing resin formed on the main surface of the wiring substrate; wherein the sealing resin may be constituted of a first resin layer filling a gap between a first face thereon the conductive bumps of the semiconductor element are formed and the main surface of the wiring substrate, and a second resin layer contacting at least circumference of the semiconductor element and formed so as to surround the semiconductor element.
Further, according to the manufacturing method of the present invention, in a manufacturing method of the flip-chip type semiconductor package, to a gap between a wiring substrate accommodated in a cavity of a molding die and a semiconductor element connected thereon, and on exterior circumference thereof, a liquid resin is injected under pressure by a transfer method or an injection molding method, by curing this, the sealing resin is formed.
Incidentally, the present invention can be applied to various kinds of semiconductor packages and semiconductor devices. For instance, the semiconductor package of the present invention also includes an MCM(multi-chip module). In addition, as a semiconductor element to be mounted, a CPU, a DSP, various kinds of memory chips including a flash type non-volatile semiconductor memory, or a composite chip thereof can be cited.